1. Field of the Invention
The present invention relates to an apparatus, method, and program for predicting layout-wiring congestion of a semiconductor integrated circuit.
2. Description of the Related Art
Various EDA (Electronic Design Automation) tools have been on the market for design tools of semiconductor integrated circuits (LSIs).
As techniques for efficiently executing automatic placement and wiring of LSIs, there have been widespread techniques for performing simulations in an environment similar to an actual state of executing placement and wiring on a chip using a net list and a cell library.
In order to perform simulations as the techniques described above, it is necessary to provide detailed physical parameters, such as the sizes of cells, the size of a chip, and the width of a wiring line.
Also, a huge amount of time is necessary for performing such a simulation using the detailed data.
Also, proposals have been made on techniques for predicting congested points of layout wiring using a net list (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2007-115159 and 2005-302062).
Japanese Unexamined Patent Application Publication No. 2007-115159 has disclosed a technique for estimating a cell which will cause wiring congestion and reducing the wiring congestion degree by prohibiting the use of the cell.
Japanese Unexamined Patent Application Publication No. 2005-302062 has disclosed a technique for reducing wiring congestion by extracting high fan-out nets on the basis of a net list and timing restriction information.